Field of the Invention
The present invention relates to a vertical transistor and, more particularly, to a vertical transistor in which an air gap is formed between the bottom S/D region and the gate structure.
Description of the Related Art
A vertical transistor or vertical field effect transistor (VFET) is a field effect transistor (FET) in which the channel region is perpendicular to the main surface of the substrate. In a VFET, the direction of the current flow between the source and drain regions is normal to the main surface of the substrate.
A typical VFET includes a vertical fin structure (e.g., a vertical fin) that extends upward from the substrate. The fin structure forms the channel region of the transistor. A source/drain (S/D) region is formed in electrical contact with the top and bottom ends of the channel region, and the gate is disposed on one or more of the side walls of the fin structure.
FIGS. 1A-1B illustrate a related art method of forming a vertical transistor (e.g., VFET).
In particular, FIG. 1A illustrates the forming of a patterned doped epitaxial layer 120 (e.g., n-type or p-type) on a substrate 110 (e.g., bulk silicon, strain-relaxed buffer (SRB) silicon germanium, etc.), and the forming of an undoped silicon layer 130 as a channel region for the vertical transistor.
FIG. 1B illustrates the patterning (e.g., etching) of the substrate 110, the patterned doped epitaxial layer 120 and the undoped silicon layer 130, using a mask 140 (e.g., silicon nitride) to form the fin structures 130f and the shallow trench isolation (STI) regions 140. Thus, the patterned doped epitaxial layer 120 will form the bottom S/D region of the related art vertical transistor.